The present disclosure is directed generally to a frequency synthesizer. A high speed acquisition system for phase locked loops to reduce component count and improve performance over a wide temperature range is disclosed in commonly owned U.S. Pat. No. 10,141,943, which is herein incorporated by reference in its entirety. The disclosed phase locked loop (PLL) has a low value of loop bandwidth and consequently low phase noise at large offsets from the carrier and may be brought into lock in a much shorter time than that normally set by the loop bandwidth. The time taken for a PLL to change frequency is inversely proportional to its loop bandwidth. Although wide loop bandwidth degrades the signal phase noise at large frequency offsets from the carrier, the digital high speed acquisition system for phase locked loops provides high speed tuning in low phase noise microwave PLLs as described hereinbelow.